Freescale Semiconductor /MK80F25615 /SDRAM /CM0

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Interpret as CM0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)V0 (0)WP 0 (0)BAM

WP=0, BAM=0, V=0

Description

Control Mask

Fields

V

Valid.

0 (0): Do not decode DRAM accesses.

1 (1): Registers controlling the DRAM block are initialized; DRAM accesses can be decoded

WP

Write protect.

0 (0): Allow write accesses

1 (1): Ignore write accesses. The DRAM controller ignores write accesses to the memory block and an address exception occurs. Write accesses to a write-protected DRAM region are compared in the chip select module for a hit. If no hit occurs, an external bus cycle is generated. If this external bus cycle is not acknowledged, an access exception occurs.

BAM

Base address mask.

0 (0): The associated address bit is used in decoding the DRAM hit to a memory block

1 (1): The associated address bit is not used in the DRAM hit decode

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